TCO
Taubman Centers Inc.
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When Lisa talks about MI355 being able to ramp more quickly than the previous generation, it's more than just the fact that the chip can slide into the same server boxes OEMs have already designed. But if that's all MI355 was, just a bit of a performance jump beyond MI325, well, the market would be justified in not taking notice. Vut here is what many are still not understanding. It's not just a performance upgrade in the GPU and VRAM, it's the ability for the chip to support the choices system builds want to use to build and scale out their networks in a way they can control their costs and investment life cycles. AMD and Broadcom are both founders of the UALink Consortium and have worked closely together on it as well as Broadcom's Scale-Up Ethernet (SUE) Framework, also discussed in the Blog. Note how the physical role out of these technologies can significantly reduce cost through repurposing of existing infrastructure.
>Physical Layer
>UALink 1.0 builds directly on IEEE Ethernet PHY technology, supporting 200 Gb/s per lane via the 212.5 Gb/s serial signaling defined by IEEE P802.3dj. Its PHY is essentially a standard Ethernet SerDes with minimal changes.
>UALink supports port speeds of 200G, 400G, and B00G, utilizing one, two, or four 200G lanes per port. Leveraging Ethernet PHY allows UALink to re-use established technologies, such as 64B/66B line encoding and KP4 Forward Error Correction (FEC), within the Physical Coding Sublayer (PCS).
>While standard Ethernet often employs a 4-way interleaved FEC for better burst-error correction, which adds latency, UALink optionally supports simpler 1-way or 2-way FEC interleaving, trading off some error correction strength for reduced latency.
>UALink thus allows vendors to reuse existing 100G/ 200G Ethernet SerDes IP and firmware with minimal modifications, which significantly lowers the development risk and total cost of ownership (TCO). It also enables the systems to utilize existing copper cables, connectors, retimers, and future optical modules developed for Ethernet.

When Lisa talks about MI355 being able to ramp more quickly than the previous generation, it's more than just the fact that the chip can slide into the same server boxes OEMs have already designed. But if that's all MI355 was, just a bit of a performance jump beyond MI325, well, the market would be justified in not taking notice. Vut here is what many are still not understanding. It's not just a performance upgrade in the GPU and VRAM, it's the ability for the chip to support the choices system builds want to use to build and scale out their networks in a way they can control their costs and investment life cycles. AMD and Broadcom are both founders of the UALink Consortium and have worked closely together on it as well as Broadcom's Scale-Up Ethernet (SUE) Framework, also discussed in the Blog. Note how the physical role out of these technologies can significantly reduce cost through repurposing of existing infrastructure.
>Physical Layer
>UALink 1.0 builds directly on IEEE Ethernet PHY technology, supporting 200 Gb/s per lane via the 212.5 Gb/s serial signaling defined by IEEE P802.3dj. Its PHY is essentially a standard Ethernet SerDes with minimal changes.
>UALink supports port speeds of 200G, 400G, and B00G, utilizing one, two, or four 200G lanes per port. Leveraging Ethernet PHY allows UALink to re-use established technologies, such as 64B/66B line encoding and KP4 Forward Error Correction (FEC), within the Physical Coding Sublayer (PCS).
>While standard Ethernet often employs a 4-way interleaved FEC for better burst-error correction, which adds latency, UALink optionally supports simpler 1-way or 2-way FEC interleaving, trading off some error correction strength for reduced latency.
>UALink thus allows vendors to reuse existing 100G/ 200G Ethernet SerDes IP and firmware with minimal modifications, which significantly lowers the development risk and total cost of ownership (TCO). It also enables the systems to utilize existing copper cables, connectors, retimers, and future optical modules developed for Ethernet.